Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64

Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
   one ARCH_EXYNOS.

This depends on clk tree: removal of last presence of ARCH_EXYNOS7.

* tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
  clk: samsung: Don't build ARMv8 clock drivers on ARMv7
  clk: samsung: Enable COMPILE_TEST for Samsung clocks
  clk: Move vendor's Kconfig into CCF menu section
  clk: mediatek: Fix memory leak on clock init fail
  clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
  clk: xgene: Remove return from void function
  clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
  Documentation: Update APM X-Gene clock binding for v2 hardware
  clk: s2mps11: remove redundant code
  clk: s2mps11: remove redundant static variables declaration
  clk: s2mps11: allocate only one structure for clock init
  clk: s2mps11: merge two for loops in one
  clk-divider: make sure read-only dividers do not write to their register
  clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
  clk: scpi: Fix checking return value of platform_device_register_simple()
  clk: mvebu: Mark ioremapped memory as __iomem

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 1 insertions, 3 deletions

diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
index 13aabbb3acbe..f7136b94fd0e 100644
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c
@@ -28,8 +28,6 @@
 #define CCU_BRANCH_IS_BUS	BIT(0)
 #define CCU_BRANCH_HAVE_DIV2	BIT(1)
 
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
 struct lpc18xx_branch_clk_data {
 	const char **name;
 	int num;
@@ -222,7 +220,7 @@ static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *bran
 		div->width = 1;
 
 		div_hw = &div->hw;
-		div_ops = &clk_divider_ops;
+		div_ops = &clk_divider_ro_ops;
 	}
 
 	branch->gate.reg = branch->offset + reg_base;