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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-09-08 17:36:50 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-09-14 10:57:07 +0300 |
| commit | b4b025246c0fbb8611a26bab121596f47f0bf116 (patch) | |
| tree | 8d8396e9d38cadad3d62638fff52231a2708ac5d /drivers/clk/microchip | |
| parent | 3ffb5ad24d0064f923ed30ad37e33e56eee31f2b (diff) | |
| download | linux-b4b025246c0fbb8611a26bab121596f47f0bf116.tar.xz | |
dt-bindings: clk: add PolarFire SoC fabric clock ids
Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
Diffstat (limited to 'drivers/clk/microchip')
0 files changed, 0 insertions, 0 deletions