diff options
| author | Michael Turquette <mturquette@baylibre.com> | 2016-06-07 09:16:17 +0300 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2016-06-23 04:02:59 +0300 |
| commit | 1c50da4f27cbfb588b59684b55eb7a087bb26ed1 (patch) | |
| tree | 476a4b396e86fb59ad46baa1e2156d25a36003aa /drivers/clk/meson/clkc.h | |
| parent | 73de5c8bcf4924faf5d57c3d626b01a04ed1ee41 (diff) | |
| download | linux-1c50da4f27cbfb588b59684b55eb7a087bb26ed1.tar.xz | |
clk: meson: add mpll support
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and
GXBB they appear to be only derived from fixed_pll.
Add support for these clock types so that they can be added to their
respective drivers.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 9436932880c0..73f014691240 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -73,6 +73,15 @@ struct meson_clk_cpu { int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event, void *data); +struct meson_clk_mpll { + struct clk_hw hw; + void __iomem *base; + struct parm sdm; + struct parm n2; + /* FIXME ssen gate control? */ + spinlock_t *lock; +}; + #define MESON_GATE(_name, _reg, _bit) \ struct clk_gate gxbb_##_name = { \ .reg = (void __iomem *) _reg, \ @@ -91,5 +100,6 @@ struct clk_gate gxbb_##_name = { \ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; extern const struct clk_ops meson_clk_cpu_ops; +extern const struct clk_ops meson_clk_mpll_ro_ops; #endif /* __CLKC_H */ |