diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-03-07 17:14:53 +0300 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-04-01 11:45:11 +0300 |
| commit | 39b8500283b45252e2f9ad9d60992f2c0d3a1659 (patch) | |
| tree | 1e2a890f2df2c981e708fc23d9268bb820e85d81 /drivers/clk/meson/clk-pll.h | |
| parent | 370294e2667fa1648eb05aab6c4657419634ff83 (diff) | |
| download | linux-39b8500283b45252e2f9ad9d60992f2c0d3a1659.tar.xz | |
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
The Meson G12A PCIE PLL is fined tuned to deliver a very precise
100MHz reference clock for the PCIe Analog PHY, and thus requires
a strict register sequence to enable the PLL.
To simplify, use the _init() op to enable the PLL and keep
the other ops except set_rate since the rate is fixed.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clk-pll.h')
| -rw-r--r-- | drivers/clk/meson/clk-pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 55af2e285b1b..367efd0f6410 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -45,5 +45,6 @@ struct meson_clk_pll_data { extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; +extern const struct clk_ops meson_clk_pcie_pll_ops; #endif /* __MESON_CLK_PLL_H */ |