diff options
| author | Remi Pommarel <repk@triplefau.lt> | 2020-03-10 00:01:56 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2021-02-09 15:32:59 +0300 |
| commit | 31035839540e3f1669f9e47222108e9278651943 (patch) | |
| tree | de1c67050817de94ecabd93b954882423850aee5 /drivers/clk/meson/axg.h | |
| parent | dcd48b25c682106335d48c040eeaaf0ff5575c38 (diff) | |
| download | linux-31035839540e3f1669f9e47222108e9278651943.tar.xz | |
clk: meson: axg: Remove MIPI enable clock gate
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 481b307ea3cb..23ea87964af2 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -16,7 +16,6 @@ * Register offsets from the data sheet must be multiplied by 4 before * adding them to the base address to get the right value. */ -#define HHI_MIPI_CNTL0 0x00 #define HHI_GP0_PLL_CNTL 0x40 #define HHI_GP0_PLL_CNTL2 0x44 #define HHI_GP0_PLL_CNTL3 0x48 |