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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-06-29 13:52:05 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-09-01 04:13:53 +0300 |
| commit | c39da7d0b40265eb4d0e9e5a1ea460ebc3f3185e (patch) | |
| tree | 3a6b69aeb6847d8d9247126b4307f7aad00e415c /drivers/clk/mediatek | |
| parent | 7e5073a74f60a3197773fa57b796a59ae40e6542 (diff) | |
| download | linux-c39da7d0b40265eb4d0e9e5a1ea460ebc3f3185e.tar.xz | |
clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220629105205.173471-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 97657f255618..ce7ac16a2f42 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -193,6 +193,8 @@ static u16 infra_ao_rst_ofs[] = { static u16 infra_ao_idx_map[] = { [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, + [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10, }; |