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| author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-09-14 05:16:15 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-09-15 01:05:37 +0300 |
| commit | 3e9121f16cb3f4f93ad7c41a644ba384d13c2945 (patch) | |
| tree | 0d8793a80926fbd5bc7a497c46221168eb1c690a /drivers/clk/mediatek/clk-mt2712-mfg.c | |
| parent | 6203815bf97eeaa78ca2e47758f0232043e69ba7 (diff) | |
| download | linux-3e9121f16cb3f4f93ad7c41a644ba384d13c2945.tar.xz | |
clk: mediatek: Add MT8195 apmixedsys clock support
Add MT8195 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt2712-mfg.c')
0 files changed, 0 insertions, 0 deletions