summaryrefslogtreecommitdiff
path: root/drivers/clk/imx/clk-pllv2.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2015-12-10 03:36:29 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2015-12-10 03:36:29 +0300
commitabb7e2b3f0714b9710b1865d2ba53525a935a7db (patch)
tree049f2fe78814e10d5536c5a4d84d0be1d6936fee /drivers/clk/imx/clk-pllv2.c
parent9a0f76fde9ad2c00c0cf13aaf3dfb9d886dc578c (diff)
parent59f0ec231f397001801264063db3b6dcc3eef590 (diff)
downloadlinux-abb7e2b3f0714b9710b1865d2ba53525a935a7db.tar.xz
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "One small build fix, a couple do_div() fixes, and a fix for the gpio basic clock type are the major changes here. There's also a couple fixes for the TI, sunxi, and scpi clock drivers" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi: pll2: Fix clock running too fast clk: scpi: add missing of_node_put clk: qoriq: fix memory leak imx/clk-pllv2: fix wrong do_div() usage imx/clk-pllv1: fix wrong do_div() usage clk: mmp: add linux/clk.h includes clk: ti: drop locking code from mux/divider drivers clk: ti816x: Add missing dmtimer clkdev entries clk: ti: fapll: fix wrong do_div() usage clk: ti: clkt_dpll: fix wrong do_div() usage clk: gpio: Get parent clk names in of_gpio_clk_setup()
Diffstat (limited to 'drivers/clk/imx/clk-pllv2.c')
-rw-r--r--drivers/clk/imx/clk-pllv2.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c
index b18f875eac6a..4aeda56ce372 100644
--- a/drivers/clk/imx/clk-pllv2.c
+++ b/drivers/clk/imx/clk-pllv2.c
@@ -79,7 +79,7 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
{
long mfi, mfn, mfd, pdf, ref_clk;
unsigned long dbl;
- s64 temp;
+ u64 temp;
dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
@@ -98,8 +98,9 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
temp = (u64) ref_clk * abs(mfn);
do_div(temp, mfd + 1);
if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
+ temp = (ref_clk * mfi) - temp;
+ else
+ temp = (ref_clk * mfi) + temp;
return temp;
}
@@ -126,7 +127,7 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
{
u32 reg;
long mfi, pdf, mfn, mfd = 999999;
- s64 temp64;
+ u64 temp64;
unsigned long quad_parent_rate;
quad_parent_rate = 4 * parent_rate;