summaryrefslogtreecommitdiff
path: root/drivers/clk/clk-stm32f4.c
diff options
context:
space:
mode:
authorGabriel Fernandez <gabriel.fernandez@st.com>2016-12-13 17:20:16 +0300
committerStephen Boyd <sboyd@codeaurora.org>2016-12-22 03:09:10 +0300
commit12696bac3ac256f4baa730b3a7b6712c602ea578 (patch)
tree994b6168016a8d41aa3f163d70b47807e0aee090 /drivers/clk/clk-stm32f4.c
parentdaf2d117cbca8913b02643aff36ec8763f7d8198 (diff)
downloadlinux-12696bac3ac256f4baa730b3a7b6712c602ea578.tar.xz
clk: stm32f4: Add I2S clock
This patch introduces I2S clock for stm32f4 soc. The I2S clock could be derived from an external clock or from pll-i2s Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-stm32f4.c')
-rw-r--r--drivers/clk/clk-stm32f4.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index fb9c4de9bb3a..fde883a73394 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -946,6 +946,8 @@ static const char *rtc_parents[4] = {
static const char *lcd_parent[1] = { "pllsai-r-div" };
+static const char *i2s_parents[2] = { "plli2s-r", NULL };
+
struct stm32_aux_clk {
int idx;
const char *name;
@@ -975,6 +977,12 @@ static const struct stm32_aux_clk stm32f429_aux_clk[] = {
STM32F4_RCC_APB2ENR, 26,
CLK_SET_RATE_PARENT
},
+ {
+ CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
+ STM32F4_RCC_CFGR, 23, 1,
+ NO_GATE, 0,
+ CLK_SET_RATE_PARENT
+ },
};
static const struct stm32f4_clk_data stm32f429_clk_data = {
@@ -1069,7 +1077,7 @@ fail:
static void __init stm32f4_rcc_init(struct device_node *np)
{
- const char *hse_clk;
+ const char *hse_clk, *i2s_in_clk;
int n;
const struct of_device_id *match;
const struct stm32f4_clk_data *data;
@@ -1104,6 +1112,10 @@ static void __init stm32f4_rcc_init(struct device_node *np)
hse_clk = of_clk_get_parent_name(np, 0);
+ i2s_in_clk = of_clk_get_parent_name(np, 1);
+
+ i2s_parents[1] = i2s_in_clk;
+
clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
16000000, 160000);
pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);