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authorKazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>2018-07-25 12:10:21 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-04-02 11:08:20 +0300
commit8d36fdcce21c1713eacf45380696f8cec3d724bf (patch)
treeaace17ba89b207615d4dae8794da0d390e8a70a6 /drivers/clk/actions
parent4aeed945b7024e454bafb4beb68b8c0298832efb (diff)
downloadlinux-8d36fdcce21c1713eacf45380696f8cec3d724bf.tar.xz
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2 Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> [takeshi: Update R-Car H3, M3-N, and E3] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update RZ/G2M and RZ/G2E] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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