serial/8250/8250_early: Prevent rounding error in uartclk

Modify divisor to select the nearest baud rate divider rather than the
lowest. It minimizes baud rate errors especially on low UART clock
frequencies.

For example, if uartclk is 33000000 and baud is 115200 the ratio is
about 17.9 The current code selects 17 (5% error) but should select 18
(0.5% error).

This 5% error in baud rate leads to garbage on receiving end, while 0.5%
doesn't.

The issue showed up when using the stock 8250 driver for
Synopsys DW UART. This was on a FPGA with ~12MHz UART clock.
When we enabled early serial, we saw garbage which was narrowed down
to the rounding error.

So the bug had been latent and it only showed up with such low clock rates.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

0 files changed, 0 insertions, 0 deletions