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| author | Olof Johansson <olof@lixom.net> | 2012-10-07 18:22:32 +0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-10-07 18:22:32 +0400 |
| commit | 0b33162ec5ce4316effd95374768b59dc6f63326 (patch) | |
| tree | 67ba1e5bcb9e3ef3cdd7f48f406983387c5421af /drivers/char/nwflash.c | |
| parent | a4ee7770c4a0eefda655bf1e19ba0eb48da828a6 (diff) | |
| parent | 45ef6ac6f5d4d4ea441a042fee3790b3f33cba73 (diff) | |
| download | linux-0b33162ec5ce4316effd95374768b59dc6f63326.tar.xz | |
Merge branch 'late/fixes' into fixes
This is a series from Arnd that fixes a number of compiler warnings
when building defconfigs on ARM.
* late/fixes:
ARM: footbridge: nw_gpio_lock is raw_spin_lock
ARM: mv78xx0: correct addr_map_cfg __initdata annotation
ARM: footbridge: remove RTC_IRQ definition
ARM: soc: dependency warnings for errata
ARM: ks8695: __arch_virt_to_dma type handling
ARM: rpc: check device_register return code in ecard_probe
ARM: davinci: don't mark da850_register_cpufreq as __init
ARM: iop13xx: fix iq81340sc_atux_map_irq prototype
ARM: iop13xx: mark iop13xx_scan_bus as __devinit
ARM: mv78xx0: mark mv78xx0_timer_init as __init_refok
ARM: s3c24xx: fix multiple section mismatch warnings
ARM: at91: unused variable in at91_pm_verify_clocks
ARM: at91: skip at91_io_desc definition for NOMMU
ARM: pxa: work around duplicate definition of GPIO24_SSP1_SFRM
ARM: pxa: remove sharpsl_fatal_check function
ARM: pxa: define palmte2_pxa_keys conditionally
ARM: pxa: Wunused-result warning in viper board file
ARM: shark: fix shark_pci_init return code
Fixed trivial conflicts in arch/arm/mach-at91/setup.c.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/char/nwflash.c')
| -rw-r--r-- | drivers/char/nwflash.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c index a0e2f7d70355..e371480d3639 100644 --- a/drivers/char/nwflash.c +++ b/drivers/char/nwflash.c @@ -583,9 +583,9 @@ static void kick_open(void) * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&nw_gpio_lock, flags); + raw_spin_lock_irqsave(&nw_gpio_lock, flags); nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); - spin_unlock_irqrestore(&nw_gpio_lock, flags); + raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... |