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authorLinus Torvalds <torvalds@linux-foundation.org>2010-09-08 01:00:43 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-09-08 01:00:43 +0400
commit4eab8a5717f5a863cb0e2fc8b22d8b22f4aaa644 (patch)
treeef1e57b99019aa876fc814d2da2560b6fab631c8 /drivers/char/agp/intel-agp.h
parent6300d6d755842f2ed18053ed6f868944d51b5aef (diff)
parent8554048070906579ec9fa19ac381deddd2d7b155 (diff)
downloadlinux-4eab8a5717f5a863cb0e2fc8b22d8b22f4aaa644.tar.xz
Merge branch 'drm-intel-fixes' of git://anongit.freedesktop.org/~ickle/drm-intel
* 'drm-intel-fixes' of git://anongit.freedesktop.org/~ickle/drm-intel: (25 commits) intel_agp,i915: Add more sandybridge graphics device ids drm/i915: Enable MI_FLUSH on Sandybridge agp/intel: Fix cache control for Sandybridge agp/intel: use #ifdef idiom for intel-agp.h agp/intel: fix physical address mask bits for sandybridge drm/i915: Prevent double dpms on drm/i915: Avoid use of uninitialised values when disabling panel-fitter drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt drm/i915: Tightly scope intel_encoder to prevent invalid use drm/i915: Allocate the PCI resource for the MCHBAR drm/i915/dp: Really try 5 times before giving up. drm/i915/sdvo: Restore guess of the DDC bus in absence of VBIOS drm/i915/dp: Boost timeout for enabling transcoder to 100ms drm/i915: Re-use set_base_atomic to share setting of the display registers drm/i915: Fix offset page-flips on i965+ drm/i915: Include a generation number in the device info i915: return -EFAULT if copy_to_user fails i915: return -EFAULT if copy_to_user fails agp/intel: Promote warning about failure to setup flush to error. drm/i915: overlay on gen2 can't address above 1G ...
Diffstat (limited to 'drivers/char/agp/intel-agp.h')
-rw-r--r--drivers/char/agp/intel-agp.h22
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 08d47532e605..ee189c74d345 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -1,6 +1,8 @@
/*
* Common Intel AGPGART and GTT definitions.
*/
+#ifndef _INTEL_AGP_H
+#define _INTEL_AGP_H
/* Intel registers */
#define INTEL_APSIZE 0xb4
@@ -200,11 +202,16 @@
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
-#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
-#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
-#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104
-#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106
-#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG 0x0126
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
+#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
/* cover 915 and 945 variants */
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -231,7 +238,8 @@
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
- agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)
#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
@@ -244,3 +252,5 @@
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
IS_SNB)
+
+#endif