summaryrefslogtreecommitdiff
path: root/drivers/ata
diff options
context:
space:
mode:
authorChen-Yu Tsai <wens@csie.org>2018-02-17 16:05:04 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-03-28 19:39:20 +0300
commitbdbd9153899061cc9aacfc376b26a2224850c61a (patch)
treeef7096127035f20cab4a4929ab05a33e396b8504 /drivers/ata
parent8f0dd27b3db01e7785038ea9a711f210067ee6ae (diff)
downloadlinux-bdbd9153899061cc9aacfc376b26a2224850c61a.tar.xz
clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops
commit 5682e268350f9eccdbb04006605c1b7068a7b323 upstream. When support for the A31/A31s CCU was first added, the clock ops for the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type, but the ops was set for div (M) clocks. This went unnoticed until now. This was because while they are different clocks, their data structures aligned in a way that ccu_div_ops would access the second ccu_div_internal and ccu_mux_internal structures, which were valid, if not incorrect. Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768 kHz clock signal to the WiFi chip. This was achievable by using the parent with the same clock rate and no divider. So the incorrect divider setting did not affect this usage. Commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP style clocks") added a new field to the ccu_mp structure, which broke the aforementioned alignment. Now the system crashes as div_ops tries to look up a nonexistent table. Reported-by: Philipp Rossak <embed3d@gmail.com> Tested-by: Philipp Rossak <embed3d@gmail.com> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/ata')
0 files changed, 0 insertions, 0 deletions