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authorTal Cohen <talcohen@habana.ai>2024-04-03 13:09:42 +0300
committerOfir Bitton <obitton@habana.ai>2024-06-23 09:53:05 +0300
commit61f4f624eaaeefcdcbef368b31960b0336e014fb (patch)
tree9dacfba03a39f09486515612d926199448bd9719 /drivers/accel/habanalabs
parent52fbab90edb7cd29490422f2073e0f8a560eb150 (diff)
downloadlinux-61f4f624eaaeefcdcbef368b31960b0336e014fb.tar.xz
accel/habanalabs: disable EQ interrupt after disabling pci
When sending disable pci msg towards firmware, there is a possibility that an EQ packet is already pending, disabling EQ interrupt will prevent this from happening. The interrupt will be re-enabled after reset. Signed-off-by: Tal Cohen <talcohen@habana.ai> Reviewed-by: Ofir Bitton <obitton@habana.ai> Signed-off-by: Ofir Bitton <obitton@habana.ai>
Diffstat (limited to 'drivers/accel/habanalabs')
-rw-r--r--drivers/accel/habanalabs/common/device.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c
index 5ca7014def00..78e65c6b76a7 100644
--- a/drivers/accel/habanalabs/common/device.c
+++ b/drivers/accel/habanalabs/common/device.c
@@ -1502,10 +1502,11 @@ static void send_disable_pci_access(struct hl_device *hdev, u32 flags)
if (hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0))
return;
- /* verify that last EQs are handled before disabled is set */
+ /* disable_irq also generates sync irq, this verifies that last EQs are handled
+ * before disabled is set. The IRQ will be enabled again in request_irq call.
+ */
if (hdev->cpu_queues_enable)
- synchronize_irq(pci_irq_vector(hdev->pdev,
- hdev->asic_prop.eq_interrupt_id));
+ disable_irq(pci_irq_vector(hdev->pdev, hdev->asic_prop.eq_interrupt_id));
}
}