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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 04:42:53 +0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 04:42:53 +0400 |
| commit | 83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 (patch) | |
| tree | bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce /crypto/async_tx/async_memset.c | |
| parent | 9308add6ea4fedeba37b0d7c4630a542bd34f214 (diff) | |
| download | linux-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.tar.xz | |
dmaengine, async_tx: support alignment checks
Some engines have transfer size and address alignment restrictions. Add
a per-operation alignment property to struct dma_device that the async
routines and dmatest can use to check alignment capabilities.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'crypto/async_tx/async_memset.c')
| -rw-r--r-- | crypto/async_tx/async_memset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index a374784e3329..58e4a8752aee 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -47,7 +47,7 @@ async_memset(struct page *dest, int val, unsigned int offset, size_t len, struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; - if (device) { + if (device && is_dma_fill_aligned(device, offset, 0, len)) { dma_addr_t dma_dest; unsigned long dma_prep_flags = 0; |