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| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2019-11-05 13:51:29 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-11-12 14:02:27 +0300 |
| commit | 7c7e53e1c93df14690bd12c1f84730fef927a6f1 (patch) | |
| tree | 6ddaadfa2d7c0ade3f98b7fb766a486077e6323e /crypto/aead.c | |
| parent | 767c7846419cc562c9dd4f14cc617c2b9b1b96cd (diff) | |
| download | linux-7c7e53e1c93df14690bd12c1f84730fef927a6f1.tar.xz | |
PCI: rcar: Fix missing MACCTLR register setting in initialization sequence
The R-Car Gen2/3 manual - available at:
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents
"RZ/G Series User's Manual: Hardware" section
strictly enforces the MACCTLR inizialization value - 39.3.1 - "Initial
Setting of PCI Express":
"Be sure to write the initial value (= H'80FF 0000) to MACCTLR before
enabling PCIETCTLR.CFINIT".
To avoid unexpected behavior and to match the SW initialization sequence
guidelines, this patch programs the MACCTLR with the correct value.
Note that the MACCTLR.SPCHG bit in the MACCTLR register description
reports that "Only writing 1 is valid and writing 0 is invalid" but this
"invalid" has to be interpreted as a write-ignore aka "ignored", not
"prohibited".
Reported-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: <stable@vger.kernel.org> # v5.2+
Diffstat (limited to 'crypto/aead.c')
0 files changed, 0 insertions, 0 deletions