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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-20 18:15:53 +0300 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-27 12:59:23 +0300 |
commit | fea89b265f78b639c4845be6b3778a2957eac4bc (patch) | |
tree | 0ab511c3403a85746fa20bc9b1605fe32c3001a0 /arch | |
parent | 124eb5dc4ca5f4beeef1c0f29f3a053a0d0f5e46 (diff) | |
download | linux-fea89b265f78b639c4845be6b3778a2957eac4bc.tar.xz |
ARM: dts: shmobile: Update CMT1 compatible values
New compatible values were introduced for the 48-bit CMT devices on
SH-Mobile AG5 and R-Mobile A1, and the old "cmt-48"-based values were
deprecated. However, the actual DTS files were never updated.
See also commits:
- 81b604c39997de91 ("dt-bindings: timer: renesas, cmt: Update CMT1 on
sh73a0 and r8a7740"),
- 8c1afba285a86b9d ("clocksource/drivers/sh_cmt: r8a7740 and sh73a0
SoC-specific match"),
- 19d608458f4f3bb3 ("clocksource/drivers/sh_cmt: Document "cmt-48" as
deprecated").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200420151553.22975-1-geert+renesas@glider.be
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/sh73a0.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ebc1ff64f530..014805894ea7 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -83,7 +83,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; + compatible = "renesas,r8a7740-cmt1"; reg = <0xe6138000 0x170>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_CMT1>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c134154bcce8..01fd06328420 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -99,7 +99,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; + compatible = "renesas,sh73a0-cmt1"; reg = <0xe6138000 0x200>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |