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| author | Marc Zyngier <maz@kernel.org> | 2021-02-24 12:37:38 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-02-24 14:35:36 +0300 |
| commit | 430251cc864beb11ac5b6d2f5c6ef54ddd432612 (patch) | |
| tree | b67d05be63028f9a9a2942d32cea0a17d9dc7322 /arch | |
| parent | 9d41053e8dc115c92b8002c3db5f545d7602498b (diff) | |
| download | linux-430251cc864beb11ac5b6d2f5c6ef54ddd432612.tar.xz | |
arm64: Add missing ISB after invalidating TLB in enter_vhe
Although there has been a bit of back and forth on the subject, it
appears that invalidating TLBs requires an ISB instruction after the
TLBI/DSB sequence when FEAT_ETS is not implemented by the CPU.
From the bible:
| In an implementation that does not implement FEAT_ETS, a TLB
| maintenance instruction executed by a PE, PEx, can complete at any
| time after it is issued, but is only guaranteed to be finished for a
| PE, PEx, after the execution of DSB by the PEx followed by a Context
| synchronization event
Add the missing ISB in enter_vhe(), just in case.
Fixes: f359182291c7 ("arm64: Provide an 'upgrade to VHE' stub hypercall")
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210224093738.3629662-4-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/hyp-stub.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index ae56787ea7c1..5eccbd62fec8 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -152,6 +152,7 @@ SYM_CODE_START_LOCAL(enter_vhe) // Invalidate TLBs before enabling the MMU tlbi vmalle1 dsb nsh + isb // Enable the EL2 S1 MMU, as set up from EL1 mrs_s x0, SYS_SCTLR_EL12 |