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authorLars Povlsen <lars.povlsen@microchip.com>2020-06-15 16:32:41 +0300
committerArnd Bergmann <arnd@arndb.de>2020-07-28 12:13:48 +0300
commite4e06a50b04296d17a4cf098a515fb452106ecf0 (patch)
treef01c7437b53f639c36dd96aae49ef5b4783d6ba2 /arch
parent39c8378a1cdf856a3671b6431f99352b75a07248 (diff)
downloadlinux-e4e06a50b04296d17a4cf098a515fb452106ecf0.tar.xz
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/microchip/sparx5.dtsi39
1 files changed, 23 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index baf4176ce1df..161846caf9c9 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -72,20 +72,29 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
- clocks: clocks {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- ahb_clk: ahb-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
- sys_clk: sys-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <625000000>;
- };
+ lcpll_clk: lcpll-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500000000>;
+ };
+
+ clks: clock-controller@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ clocks = <&lcpll_clk>;
+ reg = <0x6 0x1110000c 0x24>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <625000000>;
};
axi: axi@600000000 {
@@ -161,8 +170,6 @@
pins = "GPIO_26", "GPIO_27";
function = "uart2";
};
-
};
-
};
};