diff options
| author | Alexander Kurz <akurz@blala.de> | 2017-03-03 00:03:48 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2017-04-10 11:16:03 +0300 |
| commit | fe64d0540b32229e860c218a0267750f7344bd67 (patch) | |
| tree | cfc8dbffa87c777c95995049b9917c6adfdc00c0 /arch | |
| parent | 9f29183fa344704f7317e421d47b149ab38224f2 (diff) | |
| download | linux-fe64d0540b32229e860c218a0267750f7344bd67.tar.xz | |
ARM: dts: imx50: imx50-esdhc use imx53-esdhc
According to the reference manuals, both imx50/imx53 SOC seem to share
the same eSDHC controller, especially the section on "Multi-block Read"
mentioned in commit 361b8482026c ("mmc: sdhci-esdhc-imx: fix multiblock
reads on i.MX53") is identical for both SOC.
Hence, let imx50 use imx53-esdhc.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/imx50.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index ceae909e2201..2a98afcd8a4e 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -109,7 +109,7 @@ ranges; esdhc1: esdhc@50004000 { - compatible = "fsl,imx50-esdhc"; + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, @@ -121,7 +121,7 @@ }; esdhc2: esdhc@50008000 { - compatible = "fsl,imx50-esdhc"; + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, @@ -170,7 +170,7 @@ }; esdhc3: esdhc@50020000 { - compatible = "fsl,imx50-esdhc"; + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, @@ -182,7 +182,7 @@ }; esdhc4: esdhc@50024000 { - compatible = "fsl,imx50-esdhc"; + compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |