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| author | Robert Marko <robert.marko@sartura.hr> | 2021-11-12 16:44:02 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-01-27 13:03:40 +0300 |
| commit | 864ac5f6bfbe7d2870d5b02e2f2c5ad2e1bd9296 (patch) | |
| tree | 708515fe4d4d57d4dbe6508ce9b27ed8d9b54f21 /arch | |
| parent | 6d88a6849617c607960e79012fce36afd98c9d1a (diff) | |
| download | linux-864ac5f6bfbe7d2870d5b02e2f2c5ad2e1bd9296.tar.xz | |
arm64: dts: marvell: cn9130: add GPIO and SPI aliases
[ Upstream commit effd42600b987c1e95f946b14fefc1c7639e7439 ]
CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI
controllers built-in.
However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required
aliases as both the Orion SPI driver and MVEBU GPIO drivers require the
aliases to be present.
So add the required aliases for GPIO and SPI controllers.
Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi index a2b7e5ec979d..71769ac7f058 100644 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -11,6 +11,13 @@ model = "Marvell Armada CN9130 SoC"; compatible = "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + aliases { + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; + }; }; /* |