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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-12-09 06:45:55 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-12-09 06:45:55 +0400 |
| commit | 7d49efe2edbde8e2b585f3168fa89184893645c8 (patch) | |
| tree | 34a5bfde8ff1de0bb9640fbf1a5f42f46a249e5a /arch | |
| parent | 374b105797c3d4f29c685f3be535c35f5689b30e (diff) | |
| parent | db4ed53cfe9f5a00355891a631d47dfa3fd4541f (diff) | |
| download | linux-7d49efe2edbde8e2b585f3168fa89184893645c8.tar.xz | |
Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64
Pull ARM64 fixes from Catalin Marinas:
- Page table fixes (PROT_NONE, shareability attribute, TLB
invalidation)
- Secondary CPUs entry endianness fix
- Make NR_CPUS default to 8
* tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
arm64: mm: Fix PMD_SECT_PROT_NONE definition
arm64: Fix memory shareability attribute for ioremap_wc/cache
arm64: kernel: add code to set cpu boot mode to secondary_entry shim
arm64: make default NR_CPUS 8
arm64: ensure completion of TLB invalidatation
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm64/include/asm/io.h | 2 | ||||
| -rw-r--r-- | arch/arm64/include/asm/pgtable-hwdef.h | 2 | ||||
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 | ||||
| -rw-r--r-- | arch/arm64/mm/proc.S | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 88c8b6c1341a..6d4dd22ee4b7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -159,8 +159,7 @@ config NR_CPUS range 2 32 depends on SMP # These have to remain sorted largest to smallest - default "8" if ARCH_XGENE - default "4" + default "8" config HOTPLUG_CPU bool "Support for hot-pluggable CPUs" diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 4cc813eddacb..572769727227 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -229,7 +229,7 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot extern void __iounmap(volatile void __iomem *addr); extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); -#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY) +#define PROT_DEFAULT (pgprot_default | PTE_DIRTY) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 755f86143320..b1d2e26c3c88 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -43,7 +43,7 @@ * Section */ #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) -#define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 2) +#define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 7009387348b7..c68cca5c3523 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -282,8 +282,9 @@ ENDPROC(secondary_holding_pen) * be used where CPUs are brought online dynamically by the kernel. */ ENTRY(secondary_entry) - bl __calc_phys_offset // x2=phys offset bl el2_setup // Drop to EL1 + bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET + bl set_cpu_boot_mode_flag b secondary_startup ENDPROC(secondary_entry) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 421b99fd635d..0f7fec52c7f8 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -111,12 +111,12 @@ ENTRY(__cpu_setup) bl __flush_dcache_all mov lr, x28 ic iallu // I+BTB cache invalidate + tlbi vmalle1is // invalidate I + D TLBs dsb sy mov x0, #3 << 20 msr cpacr_el1, x0 // Enable FP/ASIMD msr mdscr_el1, xzr // Reset mdscr_el1 - tlbi vmalle1is // invalidate I + D TLBs /* * Memory region attributes for LPAE: * |