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authorJohn Crispin <blogic@openwrt.org>2016-01-04 22:23:57 +0300
committerRalf Baechle <ralf@linux-mips.org>2016-01-20 02:39:20 +0300
commitfad2522272ed5ed451d2d7b1dc547ddf3781cc7e (patch)
tree66bbb7ef467972e2a1967a794d320166f3627340 /arch
parente906a5f67e5a3337d696ec848e9c28fc68b39aa3 (diff)
downloadlinux-fad2522272ed5ed451d2d7b1dc547ddf3781cc7e.tar.xz
MIPS: ralink: fix USB frequency scaling
Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully correct. The logic for the SoC check got inverted. We need to check if it is not a MT76x8. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11992/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/ralink/mt7620.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 733768e9877c..4c17dc6e8ae9 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -459,7 +459,7 @@ void __init ralink_clk_init(void)
ralink_clk_add("10000c00.uartlite", periph_rate);
ralink_clk_add("10180000.wmac", xtal_rate);
- if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
+ if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
/*
* When the CPU goes into sleep mode, the BUS clock will be
* too low for USB to function properly. Adjust the busses