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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-09-17 05:44:54 +0400 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2012-10-04 02:12:43 +0400 |
| commit | eb9a63a1e550c489ba389c53bef0f7a94156fa8e (patch) | |
| tree | b36faff105cf9bca99931a2ffa613c0fca05b4b7 /arch/xtensa/include/asm | |
| parent | a4c8aa5e5c229be926c40f83509c8a30145802c6 (diff) | |
| download | linux-eb9a63a1e550c489ba389c53bef0f7a94156fa8e.tar.xz | |
xtensa: rename MISC SR definition to avoid name clashes
There are other special register that cause build warnings and may as
well need renaming as well.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include/asm')
| -rw-r--r-- | arch/xtensa/include/asm/regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h index d4baed246928..a3075b12aff1 100644 --- a/arch/xtensa/include/asm/regs.h +++ b/arch/xtensa/include/asm/regs.h @@ -66,7 +66,7 @@ #define ICOUNTLEVEL 237 #define EXCVADDR 238 #define CCOMPARE 240 -#define MISC 244 +#define MISC_SR 244 /* Special names for read-only and write-only interrupt registers. */ |