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author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-27 07:08:57 +0400 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-07 14:16:43 +0400 |
commit | f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 (patch) | |
tree | 9211554f0542ce636aa1f14ffe58cfa832efa04d /arch/x86 | |
parent | 93f5f7f1249e76a5e8afbdab53f90b10c41fdb61 (diff) | |
download | linux-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.tar.xz |
agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.
And set cache control to always LLC only by default on Gen6.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'arch/x86')
0 files changed, 0 insertions, 0 deletions