diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-07-24 20:34:02 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-07-25 12:21:03 +0300 |
| commit | 5b395e2be6c4621962889cb28ba2d6d1be42e39d (patch) | |
| tree | b50169db593ab0e225908f594e016f235dceb4c8 /arch/x86/pci | |
| parent | b0ee9effc17a1b52999934a73ec2ef1ddcc2bdab (diff) | |
| download | linux-5b395e2be6c4621962889cb28ba2d6d1be42e39d.tar.xz | |
x86/platform/intel-mid: Make IRQ allocation a bit more flexible
In the future we would use dynamic allocation for IRQ which brings
non-1:1 mapping for IOAPIC domain. Thus, we need to respect return value
of mp_map_gsi_to_irq() and assign it back to the device structure.
Besides that we need to read GSI from interrupt pin register to avoid
cases when some drivers will try to initialize PCI device twice in a row
which will call pcibios_enable_irq() twice as well.
serial 0000:00:04.1: Mapped GSI28 to IRQ5
serial 0000:00:04.2: Mapped GSI29 to IRQ5
serial 0000:00:04.3: Mapped GSI54 to IRQ5
8250_mid 0000:00:04.1: Mapped GSI28 to IRQ5
8250_mid 0000:00:04.2: Mapped GSI29 to IRQ6
8250_mid 0000:00:04.3: Mapped GSI54 to IRQ7
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-pci@vger.kernel.org
Link: http://lkml.kernel.org/r/20170724173402.12939-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/pci')
| -rw-r--r-- | arch/x86/pci/intel_mid_pci.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 5a18aedcb341..b901ece278dd 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -215,16 +215,23 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) struct irq_alloc_info info; int polarity; int ret; + u8 gsi; if (dev->irq_managed && dev->irq > 0) return 0; + ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); + if (ret < 0) { + dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret); + return ret; + } + switch (intel_mid_identify_cpu()) { case INTEL_MID_CPU_CHIP_TANGIER: polarity = IOAPIC_POL_HIGH; /* Special treatment for IRQ0 */ - if (dev->irq == 0) { + if (gsi == 0) { /* * Skip HS UART common registers device since it has * IRQ0 assigned and not used by the kernel. @@ -253,10 +260,11 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to * IOAPIC RTE entries, so we just enable RTE for the device. */ - ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info); + ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info); if (ret < 0) return ret; + dev->irq = ret; dev->irq_managed = 1; return 0; |