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authorYinghai Lu <yinghai@kernel.org>2009-10-05 08:54:24 +0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-11-04 19:47:09 +0300
commit99935a7a59eaca0292c1a5880e10bae03f4a5e3d (patch)
tree44d7265182ad7e1ee795a420088bc99d0096b62c /arch/x86/pci/bus_numa.h
parent91d3f9bacdb4950d2f79fe2ba296aa249f60d06c (diff)
downloadlinux-99935a7a59eaca0292c1a5880e10bae03f4a5e3d.tar.xz
x86/PCI: read root resources from IOH on Intel
For intel systems with multi IOH, we should read peer root resources directly from PCI config space, and don't trust _CRS. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/pci/bus_numa.h')
-rw-r--r--arch/x86/pci/bus_numa.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
new file mode 100644
index 000000000000..4ff126a3e887
--- /dev/null
+++ b/arch/x86/pci/bus_numa.h
@@ -0,0 +1,26 @@
+#ifdef CONFIG_X86_64
+
+/*
+ * sub bus (transparent) will use entres from 3 to store extra from
+ * root, so need to make sure we have enought slot there, Should we
+ * increase PCI_BUS_NUM_RESOURCES?
+ */
+#define RES_NUM 16
+struct pci_root_info {
+ char name[12];
+ unsigned int res_num;
+ struct resource res[RES_NUM];
+ int bus_min;
+ int bus_max;
+ int node;
+ int link;
+};
+
+/* 4 at this time, it may become to 32 */
+#define PCI_ROOT_NR 4
+extern int pci_root_num;
+extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
+
+extern void update_res(struct pci_root_info *info, size_t start,
+ size_t end, unsigned long flags, int merge);
+#endif