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authorThomas Gleixner <tglx@linutronix.de>2019-05-06 13:04:12 +0300
committerThomas Gleixner <tglx@linutronix.de>2019-05-06 13:04:12 +0300
commitfb4e0592654adb31bc6f3a738d6499b816a655d6 (patch)
treee6edaf18cf3a7f49e93fb51de5a47f4b9e786f53 /arch/x86/mm/mmap.c
parent471ba0e686cb13752bc1ff3216c54b69a2d250ea (diff)
parent16e32c3cde7763ab875b9030b443ecbc8e352d8a (diff)
downloadlinux-fb4e0592654adb31bc6f3a738d6499b816a655d6.tar.xz
Merge tag 'irqchip-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier - The huge (and terrifying) TI INTR/INTA set of drivers - Rewrite of the stm32mp1-exti driver as a platform driver - Update the IOMMU MSI mapping API to be RT friendly - A number of cleanups and other low impact fixes
Diffstat (limited to 'arch/x86/mm/mmap.c')
-rw-r--r--arch/x86/mm/mmap.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c
index db3165714521..dc726e07d8ba 100644
--- a/arch/x86/mm/mmap.c
+++ b/arch/x86/mm/mmap.c
@@ -230,7 +230,7 @@ bool mmap_address_hint_valid(unsigned long addr, unsigned long len)
/* Can we access it for direct reading/writing? Must be RAM: */
int valid_phys_addr_range(phys_addr_t addr, size_t count)
{
- return addr + count <= __pa(high_memory);
+ return addr + count - 1 <= __pa(high_memory - 1);
}
/* Can we access it through mmap? Must be a valid physical address: */