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| author | Peter Zijlstra <peterz@infradead.org> | 2022-03-08 18:30:35 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-03-15 12:32:39 +0300 |
| commit | 991625f3dd2cbc4b787deb0213e2bcf8fa264b21 (patch) | |
| tree | f328f63188d911d258d895b0f0a1a7d98ba16429 /arch/x86/include/uapi | |
| parent | 0aec21cfb51bc1856206f312d8c13bf1f368d78e (diff) | |
| download | linux-991625f3dd2cbc4b787deb0213e2bcf8fa264b21.tar.xz | |
x86/ibt: Add IBT feature, MSR and #CP handling
The bits required to make the hardware go.. Of note is that, provided
the syscall entry points are covered with ENDBR, #CP doesn't need to
be an IST because we'll never hit the syscall gap.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org
Diffstat (limited to 'arch/x86/include/uapi')
| -rw-r--r-- | arch/x86/include/uapi/asm/processor-flags.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index bcba3c643e63..c47cc7f2feeb 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -130,6 +130,8 @@ #define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT) #define X86_CR4_PKE_BIT 22 /* enable Protection Keys support */ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) +#define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ +#define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) /* * x86-64 Task Priority Register, CR8 |