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authorGrzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>2017-01-20 16:22:33 +0300
committerThomas Gleixner <tglx@linutronix.de>2017-02-04 10:51:09 +0300
commitae47eda905e61ef6ba0b6f79b967c9de15ca4f8e (patch)
tree50db24c6f7d764153a7809e5a8d146925d021088 /arch/x86/include/uapi
parent06b35d93af0a5904aa832f58733be84ddbfe2e04 (diff)
downloadlinux-ae47eda905e61ef6ba0b6f79b967c9de15ca4f8e.tar.xz
x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit
Define new MSR MISC_FEATURE_ENABLES (0x140). On supported CPUs if bit 1 of this MSR is set, then calling MONITOR and MWAIT instructions outside of ring 0 will not cause invalid-opcode exception. The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is the relevant documentation: Hex Dec Name Scope 140H 320 MISC_FEATURE_ENABLES Thread 0 Reserved 1 If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1. 63:2 Reserved Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> Cc: Piotr.Luc@intel.com Cc: dave.hansen@linux.intel.com Link: http://lkml.kernel.org/r/1484918557-15481-2-git-send-email-grzegorz.andrejczuk@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/uapi')
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