diff options
| author | Eugene Korenevsky <ekorenevsky@gmail.com> | 2014-12-11 08:53:27 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2015-01-09 00:45:15 +0300 |
| commit | e9ac033e6b6970c7061725fc6824b3933eb5a0e7 (patch) | |
| tree | d505687fd801995fdd1632b2336d53598007f30f /arch/x86/include/uapi/asm | |
| parent | ff651cb613b4cc8aa2e4284525948872b4d77d66 (diff) | |
| download | linux-e9ac033e6b6970c7061725fc6824b3933eb5a0e7.tar.xz | |
KVM: nVMX: Improve nested msr switch checking
This patch improve checks required by Intel Software Developer Manual.
- SMM MSRs are not allowed.
- microcode MSRs are not allowed.
- check x2apic MSRs only when LAPIC is in x2apic mode.
- MSR switch areas must be aligned to 16 bytes.
- address of first and last byte in MSR switch areas should not set any bits
beyond the processor's physical-address width.
Also it adds warning messages on failures during MSR switch. These messages
are useful for people who debug their VMMs in nVMX.
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/include/uapi/asm')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index c8aa65d56027..d0050f25ea80 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -356,6 +356,9 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b +#define MSR_IA32_SMBASE 0x0000009e + #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |