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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-02-12 16:24:37 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-02-12 16:24:37 +0300 |
| commit | 05fd934ba585ea8c9f129f15f11327adb1f96fe3 (patch) | |
| tree | 7b678c512c43419ccf484e71c84d69caee84a6da /arch/x86/include/asm/pci_x86.h | |
| parent | ebb7c78d358b2ea45c7d997423e6feb42e5ce4ef (diff) | |
| parent | 382ab95d1af85381d8a5dff09b16a80c7e492534 (diff) | |
| download | linux-05fd934ba585ea8c9f129f15f11327adb1f96fe3.tar.xz | |
Merge tag 'topic/drm-misc-2016-02-12' into drm-intel-next-queued
Backmerge to get at the new encoder_mask support in atomic helpers.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'arch/x86/include/asm/pci_x86.h')
| -rw-r--r-- | arch/x86/include/asm/pci_x86.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index fa1195dae425..46873fbd44e1 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -151,11 +151,11 @@ extern struct list_head pci_mmcfg_list; #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) /* - * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config - * accessor functions. - * In fact just use pci_config_*, nothing else please. + * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use + * %eax. No other source or target registers may be used. The following + * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's + * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, + * "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) { |