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authorLinus Torvalds <torvalds@linux-foundation.org>2017-02-21 01:37:08 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2017-02-21 01:37:08 +0300
commit8a9365a4725a4d6265a416dd63bff937e300308e (patch)
treeaf92e88d6e8d976080674d411850695f48d0f261 /arch/x86/include/asm/msr-index.h
parent2891e8e66787a6a5dadad017d1c8a8f23d8658af (diff)
parent3bba73b1b7a88d88c3ea16b7914c13d475e4a87b (diff)
downloadlinux-8a9365a4725a4d6265a416dd63bff937e300308e.tar.xz
Merge branch 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpufeature updates from Ingo Molnar: "The main changes in this cycle were related to enable ring-3 MONITOR/MWAIT instructions support on supported CPUs, by Grzegorz Andrejczuk and Piotr Luc" * 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpufeature: Move RING3MWAIT feature to avoid conflicts x86/cpufeature: Enable RING3MWAIT for Knights Mill x86/cpufeature: Enable RING3MWAIT for Knights Landing x86/cpufeature: Add RING3MWAIT to CPU features x86/elf: Add HWCAP2 to expose ring 3 MONITOR/MWAIT x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit x86/cpufeature: Add AVX512_VPOPCNTDQ feature
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r--arch/x86/include/asm/msr-index.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..00293a94ffaf 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -543,6 +543,11 @@
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
+/* MISC_FEATURE_ENABLES non-architectural features */
+#define MSR_MISC_FEATURE_ENABLES 0x00000140
+
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1
+
#define MSR_IA32_TSC_DEADLINE 0x000006E0
/* P4/Xeon+ specific */