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| author | Len Brown <len.brown@intel.com> | 2017-02-26 02:18:22 +0300 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-02-26 02:23:43 +0300 |
| commit | d0117a0e2780f7803fe55d543ab119416d7582e6 (patch) | |
| tree | fbcc4b179b98cc9abca96572417b709d82cd0374 /arch/x86/include/asm/msr-index.h | |
| parent | c470abd4fde40ea6a0846a2beab642a578c0b8cd (diff) | |
| download | linux-d0117a0e2780f7803fe55d543ab119416d7582e6.tar.xz | |
x86: msr-index.h: define EPB mid-points
These are currently open-coded into intel_pstate.c
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 710273c617b8..a92d9bd154f6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -462,9 +462,11 @@ #define MSR_MISC_PWR_MGMT 0x000001aa #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 -#define ENERGY_PERF_BIAS_PERFORMANCE 0 -#define ENERGY_PERF_BIAS_NORMAL 6 -#define ENERGY_PERF_BIAS_POWERSAVE 15 +#define ENERGY_PERF_BIAS_PERFORMANCE 0 +#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 +#define ENERGY_PERF_BIAS_NORMAL 6 +#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 +#define ENERGY_PERF_BIAS_POWERSAVE 15 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |