diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2015-12-12 04:45:06 +0300 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-01-07 16:11:32 +0300 |
| commit | eebb3e8d8aaf28f4bcaf12fd3645350bfd2f0b36 (patch) | |
| tree | 5d74ba65967afd6e6c1931887827a5abe66afc5d /arch/x86/include/asm/iosf_mbi.h | |
| parent | c3a49cf35ead83829e54fc771a3acc1b1aa6dfd8 (diff) | |
| download | linux-eebb3e8d8aaf28f4bcaf12fd3645350bfd2f0b36.tar.xz | |
ACPI / LPSS: override power state for LPSS DMA device
This is a third approach to workaround long standing issue with LPSS on
BayTrail. First one [1] was reverted since it didn't resolve the issue
comprehensively. Second one [2] was rejected by internal review.
The LPSS DMA controller does not have neither _PS0 nor _PS3 method. Moreover it
can be powered off automatically whenever the last LPSS device goes down. In
case of no power any access to the DMA controller will hang the system. The
behaviour is reproduced on some HP laptops based on Intel BayTrail [3,4] as
well as on ASuS T100TA transformer.
Power on the LPSS island through the registers accessible in a specific way.
[1] http://www.spinics.net/lists/linux-acpi/msg53963.html
[2] https://bugzilla.redhat.com/attachment.cgi?id=1066779&action=diff
[3] https://bugzilla.redhat.com/show_bug.cgi?id=1184273
[4] http://www.spinics.net/lists/dmaengine/msg01514.html
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'arch/x86/include/asm/iosf_mbi.h')
| -rw-r--r-- | arch/x86/include/asm/iosf_mbi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/iosf_mbi.h b/arch/x86/include/asm/iosf_mbi.h index cdc5f6352ac5..b41ee164930a 100644 --- a/arch/x86/include/asm/iosf_mbi.h +++ b/arch/x86/include/asm/iosf_mbi.h @@ -19,6 +19,8 @@ /* IOSF SB read/write opcodes */ #define MBI_MMIO_READ 0x00 #define MBI_MMIO_WRITE 0x01 +#define MBI_CFG_READ 0x04 +#define MBI_CFG_WRITE 0x05 #define MBI_CR_READ 0x06 #define MBI_CR_WRITE 0x07 #define MBI_REG_READ 0x10 |