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| author | Borislav Petkov (AMD) <bp@alien8.de> | 2023-07-18 12:13:40 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-08-08 20:57:40 +0300 |
| commit | df76a59feba549825f426cb1586bfa86b49c08fa (patch) | |
| tree | 5ba84988625438df25f34a40cad40baa1632a914 /arch/x86/include/asm/cpufeatures.h | |
| parent | 3f9b7101bea1dcb63410c016ceb266f6e9f733c9 (diff) | |
| download | linux-df76a59feba549825f426cb1586bfa86b49c08fa.tar.xz | |
x86/srso: Add IBPB_BRTYPE support
Upstream commit: 79113e4060aba744787a81edb9014f2865193854
Add support for the synthetic CPUID flag which "if this bit is 1,
it indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch
type predictions from the CPU branch predictor."
This flag is there so that this capability in guests can be detected
easily (otherwise one would have to track microcode revisions which is
impossible for guests).
It is also needed only for Zen3 and -4. The other two (Zen1 and -2)
always flush branch type predictions by default.
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index f54207b90cad..2c43af9e836c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -402,6 +402,8 @@ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */ + /* * BUG word(s) */ |