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| author | Peter Zijlstra (Intel) <peterz@infradead.org> | 2019-03-06 00:23:17 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2019-03-06 11:25:41 +0300 |
| commit | 52f64909409c17adf54fcf5f9751e0544ca3a6b4 (patch) | |
| tree | e61af1fcb70735394b1269070d5a763c52cf604c /arch/x86/events/intel | |
| parent | 11f8b2d65ca9029591c8df26bb6bd063c312b7fe (diff) | |
| download | linux-52f64909409c17adf54fcf5f9751e0544ca3a6b4.tar.xz | |
x86: Add TSX Force Abort CPUID/MSR
Skylake systems will receive a microcode update to address a TSX
errata. This microcode will (by default) clobber PMC3 when TSX
instructions are (speculatively or not) executed.
It also provides an MSR to cause all TSX transaction to abort and
preserve PMC3.
Add the CPUID enumeration and MSR definition.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/events/intel')
0 files changed, 0 insertions, 0 deletions