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authorVignesh R <vigneshr@ti.com>2018-10-15 09:38:28 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-12-01 11:13:43 +0300
commit9fa14d7b75f6accd4cedf360d2fb190012f02f8b (patch)
treea2d381a5aecbd0bdf538a4d740875870a4deb134 /arch/sparc
parent156c7d83c90de9d8afd5a5bd8b4536c38bda7939 (diff)
downloadlinux-9fa14d7b75f6accd4cedf360d2fb190012f02f8b.tar.xz
spi: omap2-mcspi: Set FIFO DMA trigger level to word length
[ Upstream commit b682cffa3ac6d9d9e16e9b413c45caee3b391fab ] McSPI has 32 byte FIFO in Transmit-Receive mode. Current code tries to configuration FIFO watermark level for DMA trigger to be GCD of transfer length and max FIFO size which would mean trigger level may be set to 32 for transmit-receive mode if length is aligned. This does not work in case of SPI slave mode where FIFO always needs to have data ready whenever master starts the clock. With DMA trigger size of 32 there will be a small window during slave TX where DMA is still putting data into FIFO but master would have started clock for next byte, resulting in shifting out of stale data. Similarly, on Slave RX side there may be RX FIFO overflow Fix this by setting FIFO watermark for DMA trigger to word length. This means DMA is triggered as soon as FIFO has space for word length bytes and DMA would make sure FIFO is almost always full therefore improving FIFO occupancy in both master and slave mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/sparc')
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