diff options
| author | Jens Axboe <jens.axboe@oracle.com> | 2009-12-03 15:49:39 +0300 |
|---|---|---|
| committer | Jens Axboe <jens.axboe@oracle.com> | 2009-12-03 15:49:39 +0300 |
| commit | 220d0b1dbf78c6417a658c96e571415552d3abac (patch) | |
| tree | 70cd3862540c38ea490e7a27c3c7acc35b680234 /arch/sparc/include/asm | |
| parent | 474b18ccc264c472abeec50f48469b6477202699 (diff) | |
| parent | 22763c5cf3690a681551162c15d34d935308c8d7 (diff) | |
| download | linux-220d0b1dbf78c6417a658c96e571415552d3abac.tar.xz | |
Merge branch 'master' into for-2.6.33
Diffstat (limited to 'arch/sparc/include/asm')
| -rw-r--r-- | arch/sparc/include/asm/system_64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad7..d47a98e66972 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h @@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ : : : "memory"); \ } while (0) +/* The kernel always executes in TSO memory model these days, + * and furthermore most sparc64 chips implement more stringent + * memory ordering than required by the specifications. + */ #define mb() membar_safe("#StoreLoad") #define rmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory") |