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authorDan Williams <dan.j.williams@intel.com>2010-05-18 03:30:58 +0400
committerDan Williams <dan.j.williams@intel.com>2010-05-18 03:30:58 +0400
commit0b28330e39bbe0ffee4c56b09fc415fcec595ea3 (patch)
treefcf504879883763557e696eff81427b1ab78f76b /arch/sh/mm/tlb-sh3.c
parent058276303dbc4ed089c1f7dad0871810b1f5ddf1 (diff)
parentcaa20d974c86af496b419eef70010e63b7fab7ac (diff)
downloadlinux-0b28330e39bbe0ffee4c56b09fc415fcec595ea3.tar.xz
Merge branch 'ioat' into dmaengine
Diffstat (limited to 'arch/sh/mm/tlb-sh3.c')
-rw-r--r--arch/sh/mm/tlb-sh3.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 4f5f7cbdd508..7a940dbfc2e9 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
for (i = 0; i < ways; i++)
__raw_writel(data, addr + (i << 8));
}
+
+void local_flush_tlb_all(void)
+{
+ unsigned long flags, status;
+
+ /*
+ * Flush all the TLB.
+ *
+ * Write to the MMU control register's bit:
+ * TF-bit for SH-3, TI-bit for SH-4.
+ * It's same position, bit #2.
+ */
+ local_irq_save(flags);
+ status = __raw_readl(MMUCR);
+ status |= 0x04;
+ __raw_writel(status, MMUCR);
+ ctrl_barrier();
+ local_irq_restore(flags);
+}