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| author | Jisheng Zhang <jszhang@kernel.org> | 2022-10-02 07:49:31 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-10-02 07:49:31 +0300 |
| commit | b60ca69715fcc39a5f4bdd56ca2ea691b7358455 (patch) | |
| tree | ff604f4535c6fe3786500ce8815aa8994aa6e761 /arch/riscv | |
| parent | 9c00fbdd93a22a6657378292f2eb29e9754cde7f (diff) | |
| download | linux-b60ca69715fcc39a5f4bdd56ca2ea691b7358455.tar.xz | |
riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Move POSIX CPU timer expiry and signal delivery into task context to
allow PREEMPT_RT setups to coexist with KVM.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d6b0ffd9bf00..74082e2d7ce8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -103,6 +103,7 @@ config RISCV select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP + select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_STACKPROTECTOR |