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| author | Andrew Jones <ajones@ventanamicro.com> | 2023-08-04 16:56:18 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-08-08 14:56:05 +0300 |
| commit | 630b4cee9c378e2dbb56ed84f71fc2fac50b716e (patch) | |
| tree | a630bb101e1ccf955adabdc17fbab9aae9a492cf /arch/riscv/kvm/vcpu_onereg.c | |
| parent | e47f3c2843c2c23467f9447ed977dfccbe13a6f7 (diff) | |
| download | linux-630b4cee9c378e2dbb56ed84f71fc2fac50b716e.tar.xz | |
RISC-V: KVM: Improve vector save/restore functions
Make two nonfunctional changes to the vector get/set vector reg
functions and their supporting function for simplification and
readability. The first is to not pass KVM_REG_RISCV_VECTOR, but
rather integrate it directly into the masking. The second is to
rename reg_val to reg_addr where and address is used instead of
a value.
Also opportunistically touch up some of the code formatting for
a third nonfunctional change.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/vcpu_onereg.c')
| -rw-r--r-- | arch/riscv/kvm/vcpu_onereg.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 989ea32dbcbe..9fee1c176fbb 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -645,8 +645,7 @@ int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_SBI_EXT: return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg); case KVM_REG_RISCV_VECTOR: - return kvm_riscv_vcpu_set_reg_vector(vcpu, reg, - KVM_REG_RISCV_VECTOR); + return kvm_riscv_vcpu_set_reg_vector(vcpu, reg); default: break; } @@ -677,8 +676,7 @@ int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_SBI_EXT: return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg); case KVM_REG_RISCV_VECTOR: - return kvm_riscv_vcpu_get_reg_vector(vcpu, reg, - KVM_REG_RISCV_VECTOR); + return kvm_riscv_vcpu_get_reg_vector(vcpu, reg); default: break; } |