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| author | Yash Shah <yash.shah@sifive.com> | 2019-05-06 13:48:40 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-17 06:42:13 +0300 |
| commit | a967a289f16969527a8a41e261695c639a69bee4 (patch) | |
| tree | eda00cc7ecc719a9ed5e9cb82d27b64fb929d4fa /arch/riscv/include | |
| parent | 5545b6d1ba25ce4a3a339b1edb760e666e693599 (diff) | |
| download | linux-a967a289f16969527a8a41e261695c639a69bee4.tar.xz | |
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
The driver currently supports only SiFive FU540-C000 platform.
The initial version of L2 cache controller driver includes:
- Initial configuration reporting at boot up.
- Support for ECC related functionality.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/sifive_l2_cache.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/arch/riscv/include/asm/sifive_l2_cache.h new file mode 100644 index 000000000000..04f6748fc50b --- /dev/null +++ b/arch/riscv/include/asm/sifive_l2_cache.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SiFive L2 Cache Controller header file + * + */ + +#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H +#define _ASM_RISCV_SIFIVE_L2_CACHE_H + +extern int register_sifive_l2_error_notifier(struct notifier_block *nb); +extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); + +#define SIFIVE_L2_ERR_TYPE_CE 0 +#define SIFIVE_L2_ERR_TYPE_UE 1 + +#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */ |