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authorChristophe Leroy <christophe.leroy@c-s.fr>2018-11-29 17:07:21 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2018-12-04 11:45:01 +0300
commit55c8fc3f4930286580af98711a481f35fa564e42 (patch)
tree72aec6a363562541e08d4a0bc94b30bcab3298e1 /arch/powerpc/sysdev/scom.c
parent3fb69c6a1a13afc5f64ef84e96d69a4be199d485 (diff)
downloadlinux-55c8fc3f4930286580af98711a481f35fa564e42.tar.xz
powerpc/8xx: reintroduce 16K pages with HW assistance
Using this HW assistance implies some constraints on the page table structure: - Regardless of the main page size used (4k or 16k), the level 1 table (PGD) contains 1024 entries and each PGD entry covers a 4Mbytes area which is managed by a level 2 table (PTE) containing also 1024 entries each describing a 4k page. - 16k pages require 4 identifical entries in the L2 table - 512k pages PTE have to be spread every 128 bytes in the L2 table - 8M pages PTE are at the address pointed by the L1 entry and each 8M page require 2 identical entries in the PGD. In order to use hardware assistance with 16K pages, this patch does the following modifications: - Make PGD size independent of the main page size - In 16k pages mode, redefine pte_t as a struct with 4 elements, and populate those 4 elements in __set_pte_at() and pte_update() - Adapt the size of the hugepage tables. - Define a PTE_FRAGMENT_NB so that a 16k page contains 4 page tables. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/sysdev/scom.c')
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