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| author | Andre Schwarz <andre.schwarz@matrix-vision.de> | 2008-07-10 13:53:16 +0400 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2008-07-12 22:10:12 +0400 |
| commit | 6eb9d32298290b956693fd85c815b817d39a9505 (patch) | |
| tree | 96799533e195fdac4f4e19f5cbdd204bfd9899cf /arch/powerpc/sysdev/fsl_soc.c | |
| parent | 0db9360aaa9b95b0cf67f82874809f16e68068eb (diff) | |
| download | linux-6eb9d32298290b956693fd85c815b817d39a9505.tar.xz | |
powerpc/mpc5200: PCI write combine timer
On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is
initialized with only bit 7 (Latrule disable) set. The 8-Bit write
combine timer (Bits 24..31) should be also set to a reasonable value
_greater zero_ (0x08 = default) since setting it to 0x00 leads to
_very poor_ performance as a PCI target since external burst won't be
possible at all.
Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_soc.c')
0 files changed, 0 insertions, 0 deletions