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authorJustin P. Mattock <justinmattock@gmail.com>2010-12-31 03:09:40 +0300
committerJiri Kosina <jkosina@suse.cz>2011-01-03 18:10:41 +0300
commit8dd11f80ab73fa6d47f4a9aabb5cee7bc69e7f7a (patch)
tree5e7c3d1f7b2420e12ebeb99980f48c60c953b361 /arch/powerpc/platforms/85xx/mpc85xx_mds.c
parent48e34d0f4f357bb24fa4c6f84a93b9b8349db722 (diff)
downloadlinux-8dd11f80ab73fa6d47f4a9aabb5cee7bc69e7f7a.tar.xz
ppc: fix comment typo singal -> signal
The patches below fixes a typo "singal" to "signal". Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_mds.c')
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index aa34cac4eb5c..747d1ee661fd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -309,7 +309,7 @@ static void __init mpc85xx_mds_qe_init(void)
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
- * and QE12 for QE MII management singals in PMUXCR
+ * and QE12 for QE MII management signals in PMUXCR
* register.
*/
setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |