diff options
| author | Takashi Iwai <tiwai@suse.de> | 2009-03-17 11:28:13 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2009-03-17 11:28:13 +0300 |
| commit | 37ba1b62836d2440980cf553c49556393b05c6cd (patch) | |
| tree | 3bbd9b76117d484d5a624db1b2b9ec0181c7ff55 /arch/powerpc/platforms/52xx/mpc52xx_pci.c | |
| parent | 1713c0d508fbbb42aa5f90039195e5ac31a50625 (diff) | |
| parent | dde332b660cf0bc2baaba678b52768a0fb6e6da2 (diff) | |
| download | linux-37ba1b62836d2440980cf553c49556393b05c6cd.tar.xz | |
Merge branch 'fix/opl3sa2-suspend' into topic/isa-misc
Diffstat (limited to 'arch/powerpc/platforms/52xx/mpc52xx_pci.c')
| -rw-r--r-- | arch/powerpc/platforms/52xx/mpc52xx_pci.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c index c3f2c21024e3..87ff522f28b5 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c @@ -20,14 +20,6 @@ /* ======================================================================== */ -/* PCI windows config */ -/* ======================================================================== */ - -#define MPC52xx_PCI_TARGET_IO 0xf0000000 -#define MPC52xx_PCI_TARGET_MEM 0x00000000 - - -/* ======================================================================== */ /* Structures mapping & Defines for PCI Unit */ /* ======================================================================== */ @@ -244,7 +236,7 @@ static struct pci_ops mpc52xx_pci_ops = { static void __init mpc52xx_pci_setup(struct pci_controller *hose, - struct mpc52xx_pci __iomem *pci_regs) + struct mpc52xx_pci __iomem *pci_regs, phys_addr_t pci_phys) { struct resource *res; u32 tmp; @@ -314,10 +306,14 @@ mpc52xx_pci_setup(struct pci_controller *hose, /* Set all the IWCR fields at once; they're in the same reg */ out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2)); - out_be32(&pci_regs->tbatr0, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO ); - out_be32(&pci_regs->tbatr1, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM ); + /* Map IMMR onto PCI bus */ + pci_phys &= 0xfffc0000; /* bar0 has only 14 significant bits */ + out_be32(&pci_regs->tbatr0, MPC52xx_PCI_TBATR_ENABLE | pci_phys); + out_be32(&pci_regs->bar0, PCI_BASE_ADDRESS_MEM_PREFETCH | pci_phys); + + /* Map memory onto PCI bus */ + out_be32(&pci_regs->tbatr1, MPC52xx_PCI_TBATR_ENABLE); + out_be32(&pci_regs->bar1, PCI_BASE_ADDRESS_MEM_PREFETCH); out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); @@ -414,7 +410,7 @@ mpc52xx_add_bridge(struct device_node *node) /* Finish setting up PCI using values obtained by * pci_proces_bridge_OF_ranges */ - mpc52xx_pci_setup(hose, pci_regs); + mpc52xx_pci_setup(hose, pci_regs, rsrc.start); return 0; } |