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| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2024-08-20 20:23:48 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2024-08-30 14:29:52 +0300 |
| commit | 1a736d98c84acd38e40fff69528ce7aaa55dd22d (patch) | |
| tree | 6b2002f327586ae35bbf94c14d0e1a3b39360ce4 /arch/powerpc/mm | |
| parent | 985db026c34dfc45213649023d5505822a5dcd78 (diff) | |
| download | linux-1a736d98c84acd38e40fff69528ce7aaa55dd22d.tar.xz | |
Revert "powerpc/8xx: Always pin kernel text TLB"
This reverts commit bccc58986a2f98e3af349c85c5f49aac7fb19ef2.
When STRICT_KERNEL_RWX is selected, EXEC memory must stop where
RW memory start. When pinning iTLBs it means an 8M alignment for
RW data start. That may be acceptable on boards with a lot of
memory but one of my supported boards only has 32 Mbytes and this
forced alignment leads to a waste of almost 4 Mbytes with is more
than 10% of the total memory.
So revert commit bccc58986a2f ("powerpc/8xx: Always pin kernel text
TLB") but don't restore previous behaviour in ITLB miss handler
as now kernel PGD entries are copied into each process PGDIR.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/01b6780b860c8043b51a1ba9d83acfc6f2dde910.1724173828.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/nohash/8xx.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index 15d918dce27d..4c2f9d716993 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -177,7 +177,8 @@ int mmu_mark_initmem_nx(void) if (!debug_pagealloc_enabled_or_kfence()) err = mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false); - mmu_pin_tlb(block_mapped_ram, false); + if (IS_ENABLED(CONFIG_PIN_TLB_TEXT)) + mmu_pin_tlb(block_mapped_ram, false); return err; } |