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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-01-27 19:48:30 +0300 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-01-27 19:48:30 +0300 |
| commit | 701ddf0bbfc761b8bdc974ce9c4e05f9833683e3 (patch) | |
| tree | 1009975aacf14d36cc280dfeef1a9a816fa16ef8 /arch/powerpc/lib/string_32.S | |
| parent | 0dcf2572710d68c305e58946c435ddf67ea16bf3 (diff) | |
| parent | ccfb9299a0b63da4fde607c822e1470472a46177 (diff) | |
| download | linux-701ddf0bbfc761b8bdc974ce9c4e05f9833683e3.tar.xz | |
Merge tag 'spi-nor/for-5.6' into mtd/next
SPI NOR core changes:
- Add support for TB selection using SR bit 6,
- Add support for few flashes.
Diffstat (limited to 'arch/powerpc/lib/string_32.S')
| -rw-r--r-- | arch/powerpc/lib/string_32.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/lib/string_32.S b/arch/powerpc/lib/string_32.S index f69a6aab7bfb..1ddb26394e8a 100644 --- a/arch/powerpc/lib/string_32.S +++ b/arch/powerpc/lib/string_32.S @@ -17,7 +17,7 @@ CACHELINE_BYTES = L1_CACHE_BYTES LG_CACHELINE_BYTES = L1_CACHE_SHIFT CACHELINE_MASK = (L1_CACHE_BYTES-1) -_GLOBAL(__clear_user) +_GLOBAL(__arch_clear_user) /* * Use dcbz on the complete cache lines in the destination * to set them to zero. This requires that the destination @@ -87,4 +87,4 @@ _GLOBAL(__clear_user) EX_TABLE(8b, 91b) EX_TABLE(9b, 91b) -EXPORT_SYMBOL(__clear_user) +EXPORT_SYMBOL(__arch_clear_user) |